The present invention is generally related to complementary-metal-oxide-semiconductor (CMOS) integrated circuits for voltage comparator applications. More particularly, the present invention is directed to the reduction of input voltage offsets in a switched capacitor differential input stage, thereby providing a voltage comparator circuit specifically adapted for use in precision analog-to-digital (A/D) conversion and zero-crossing detection applications.
An input voltage offset in a differential amplifier refers to the amount of input voltage that must be applied to one input terminal in order to produce a zero output voltage. Offsets can be attributed to geometry variations, mobility mismatches, impurity concentration variations, and mismatches in device thresholds from transistor-totransistor. The input voltage offset, if multiplied by the gain of the differential amplifier stage, would be a measure of the output voltage offset. For example, a 5 millivolt input voltage offset in an amplifier with an open loop gain of 1000 causes five volts at the output terminal in the absence of an input signal. Even a relatively small voltage offset, when multiplied by the gain of the differential amplifier stage, could saturate the amplifier stage during operation. Closing the feedback loop reduces the magnitude of the output offset voltage, but signal gain is also reduced.
Various attempts have been made in the prior art to eliminate these offset errors in MOS integrated circuits. Cooperman, in U.S. Pat. No. 4,255,715, requires numerous correction cycles to couple the output voltage offset to a storage capacitor via an external offset correction circuit. Many applications preclude the use of this technique due to the significant initialization time delays necessary on power-up.
A variation on the switched capacitor type of offse correction circuit is presented in the article entitled, "An NMOS Comparator for a Bubble Memory", IEEE Journal of SolidState Circuits, Vol. SC-16, No. 6, December 1981, by J.L. McCreary and J.B. Hunt. In this approach, the input capacitors are initialized to bias the differential input stage to the proper operating point. This is accomplished through the use of clamp or bias switches connected to an external DC bias voltage source. However, to reduce the input transistor offsets, the prior art relies upon staggered clock techniques and multiple gain stages.
Hence, these prior art techniques fail to effectively solve the offset voltage problem inherent in CMOS integrated circuit differential comparators. An effective solution must also consider fabrication cost limitations and integrated circuit area requirements. A need, therefore, exists for an improved voltage comparator which addresses these issues.